1. Field of the Invention
This invention relates generally to computer systems, and more particularly to memory control within a system that includes cache memory.
2. Discussion of the Related Art
It has become increasingly desirable to increase the speed with which computers process information. Two schemes for increasing processing speed include improving memory access time and using multiple processors.
A common manner in which to improve memory access time is to provide a cache memory along with a main memory. A cache memory is typically associated with a processor, and requires less access time than the main memory. A cache memory that is associated with a particular processor may also be referred to as a local cache. Copies of data from reads and writes from the processor are retained in the cache. Some cache systems retain recent reads and writes, while others may have more complex algorithms to determine which data is retained in the cache memory. When a processor requests a data read for data which is currently in the cache, only the cache memory is accessed. Since the cache memory requires less access time than the main memory, processing speed is improved.
Additionally, a cache system may be used to increase the effective speed of a data write. For example, if a processor is to write to a data location, the processor may perform a data write only to the cache memory. The cache memory and associated control logic may then write the data to the main memory while the processor proceeds with other tasks.
The use of multiple processors may also improve the effective speed by which a computer operates. In a multiple processor arrangement, several processors may simultaneously perform related functions in order to decrease the overall time required to perform those functions. In many cases, it is advantageous for the several processors to share a common bus and a common main memory, so that data to be transferred among the several processors may be quickly communicated.
However, if a cache system is to be combined with a multiple processor arrangement, there is a possibility that one of the caches associated with one of the processors may contain data required by another of the processors. In such an instance, the processor that requires the data may receive "stale" or old data from the memory. Furthermore, if a memory is responding to several read and write requests from multiple processors that have cache memories, there is a possibility that data corresponding to a particular read request has already been updated in one of the caches. It is also possible that the data corresponding to a particular read request has a pending write request that has not yet been actually written. This situation may also result in stale data being returned to the processor in response to a read request.